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8-bit Register

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Width
8 bits
Latency
unknown
Blocks
2622
Size, H×W×D
19×6×23
Works from
Alpha

Failed verification

  • Gives wrong outputs for some inputsFix: See which cases fail under Simulation, fix the circuit, and upload it as a new version.
  • Doesn't hold: 2 of 12 cases wrongFix: See which cases fail under Simulation, fix the circuit, and upload it as a new version.

Unverified specs

Category
Register fails simulation
Stateless
No unverified

Credits

Builder
embizone
Built
October 17, 2026
Uploaded by
embizone
File
Name
8_bit_Register.schem
Uploaded
October 17, 2026
Downloads
2
Conventions
followed

Inputs and outputs

InputBitsPower
data in8hard
write 1–22 lineshard
read 1–22 linessoft
OutputBits
data out8
Block distribution
Solid
671
Dust
467
Torch
185
Lever
10
Button
2

Description

First ever 3 wide vertical alpha registers.

Simulation

106 of 768 cases wrong

each of 2 cells written, then read, every combination.

Cells

Cells
CellWriteRead
1(5, 1, 19)(6, 0, 6)
2(2, 2, 19)(3, 1, 6)

Faults

Faults
FaultStepCellValueExpected
1write211111111255
read211111111255
write1000000102
read21111111025411111111255

Wrong bits

  • output bit 1, in 32 cases
  • output bit 2, in 32 cases
  • output bit 3, in 32 cases
  • output bit 4, in 32 cases
  • output bit 5, in 32 cases
  • output bit 6, in 32 cases

First wrong cases

First wrong cases
OperationAoutput
cell 2 read10100010162
got10100000160expected10100010162
cell 2 read10100110166
got10100010162expected10100110166
cell 2 read10101010170
got10101000168expected10101010170
cell 2 read10101100172
got10101000168expected10101100172
cell 2 read10101110174
got10100110166expected10101110174